1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection technology, more specifically, to a substrate-triggered lateral bipolar junction transistor (STLBJT) for use in ESD protection and the related ESD protection circuit.
2. Description of the Prior Art
ESD phenomena have become a reliability issue in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) because of technology scaling and high frequency requirements. For radio frequency (RF) ICs, the on-chip ESD protection design suffers from several limitations, such as low parasitic capacitance, constant input capacitance, insensitivity to substrate coupling noises, and high ESD robustness. A typical requirement of the maximal loading capacitance for an RF input pad is only 200 fF at an operating frequency of 2 GHz. As described herein, this 200 fF target not only includes ESD protection devices but also the bond pad itself. In order to fulfill these requirements, diodes are commonly used for ESD protection in I/O circuits. To deal with these challenges, low-capacitance bond pad and low-capacitance ESD protection circuitry had been proposed with some specific techniques.
Moreover, by adding a turn-on efficient ESD clamp circuit across the power rails of the input ESD protection circuit formed by the diodes, the overall ESD level of the input pin can be significantly improved. FIG. 1 is a circuit diagram of a conventional input ESD protection circuit with a power-rail (VDD-to-VSS) ESD clamp circuit. In FIG. 1, ESD diodes Dp1 and Dn1 are connected to pad 10 and ESD diodes Dp2 and Dn2 are connected to pad 12. Numeral 14 represents an internal circuit and numeral 16 represents the ESD clamp circuit connected between the VDD and VSS power rails. When the ESD pulse is applied to pad 10 and pad 12 is relatively grounded, the ESD current is conducted to the power rail VDD through the forward-biased ESD diode Dp1. The ESD current on the VDD power rail is discharged to the VSS power rail by the efficient VDD-to-VSS ESD clamp circuit 16. Finally, the ESD current is conducted to grounded pad 2 through the forward-biased ESD diode Dn2. The overall discharging path of the ESD current is indicated by a bold line 18 in FIG. 1. By using such ESD protection design, the ESD diodes are all operating in the forward-biased condition to discharge the ESD current. The diode operated in the forward-biased condition can sustain a much higher ESD level with a small device dimension. Thus, the ESD clamp device in the input ESD protection circuit can be realized with smaller device dimensions to significantly reduce the input capacitance of the input ESD protection circuit for high-frequency applications.
Therefore, the turn-on efficient power-rail ESD clamp circuit can significantly improve the ESD robustness of IC products if the power-rail ESD clamp circuit can be turned on efficiently while an ESD event is happening.
In addition, U.S. Pat. No. 5,744,842 disclosed an area-efficient VDD-to-VSS ESD protection circuit. FIG. 2 is a circuit diagram of this ESD protection circuit and FIG. 3 is a cross-section of the ESD protection circuit.
As shown in FIG. 2 and FIG. 3, the ESD protection circuit is composed of an ESD transient detection circuit 102 and an N-type field oxide device 100. The ESD transient detection circuit 102 comprises a resistance-capacitance network, which includes a resistor R and a capacitor C and is connected between the VDD and VSS power rails, and an inverter 104 including a PMOS transistor Mp and an NMOS transistor Mn. The field oxide device 100 is a parasitic bipolar junction device including an N+ collector 302, N+ emitter 304 and a P+ base 300. The RC network has a delay constant longer than the duration of the electrostatic pulse and shorter than the duration of the rising time of VDD power-on. The contact of the resistor R and the capacitor C is electrically coupled to the input of inverter 104. The gate of PMOS transistor Mp is coupled to the gate of NMOS transistor Mn. The sources of PMOS transistor Mp and NMOS transistor Mn are coupled to the VDD and VSS power lines, respectively. The drains of PMOS transistor Mp and NMOS transistor Mn are coupled to base 300 of the field oxide device 100. When the ESD pulse occurs on the VDD power line and the VSS power line is relatively grounded, the gates of PMOS transistor Mp and NMOS transistor Mn maintain a low voltage level since the RC network has a longer delay time constant. Thus, PMOS transistor Mp turns on and NMOS transistor Mn turns off. The initial ESD current flows into the base 300 of the field oxide device 100 through PMOS transistor Mp and then flows to the VSS power line through the substrate pickup 308. At the same time, the initial ESD current raises the base voltage of the parasitic BJT and triggers on the parasitic BJT. Then, the ESD current on the VDD power line flows to the VSS power line through the parasitic BJT.
In '842, the base of the parasitic BJT is defined by a field oxide. However, field oxide can be replaced by shallow trench isolation (STI) in sub-quarter-micron CMOS process because of bird's beak effect of the field oxide. The STI is deeper than the field oxide in silicon substrate. Therefore, the field oxide device in STI technology is hard to turn on.
U.S. Pat. No. 5,581,104 disclosed a grounded-base BJT device serving as an ESD protection device. This grounded-base BJT structure includes a parasitic diode used to aid the triggering of the BJT.
In the above, the power-rail ESD clamp circuit is important to improve the ESD robustness of IC products. As well, the power-rail ESD clamp circuit needs to be triggered efficiently while an ESD event is happening. However, the field oxide device in sub-quarter-micron CMOS process using the STI technology is hard to turn on.
Therefore, the object of the present invention is to provide an ESD protection device and an ESD protection circuit using the same, which has a lower triggering voltage and can be triggered more efficiently as the ESD event occurs, especially in the sub-quarter-micron CMOS process.